M7040N データシートの表示（PDF） - STMicroelectronics

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M7040N

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M7040N

COMMAND CODES AND PARAMETERS

A master device, such as an ASIC controller, is-

sues commands to the M7040N using the Com-

mand Valid CMDV signal and the CMD Bus. The

following subsections describe the functions of the

commands.

Command Codes

The M7040N implements four basic commands

shown in Table 17. The Command Code must be

presented to CMD[1:0] while keeping the com-

mand valid (CMDV) signal high for two CLK2X cy-

cles. These two CLK2X cycles are designated as

“Cycle A” and “Cycle B” when the CLK_MODE pin

is low. In CLK2X mode, the controller ASIC must

align the instructions with the PHS_L signal. The

command code must be presented to CMD[1:0]

while keeping the CMDV signal high for one

CLK1X cycle when the CLK_MODE pin is high. In

CLK1X mode the high phase of the CLK1X is des-

ignated as Cycle A and the low phase of the

CLK1X is designated as Cycle B. The CMD[10:2]

field passes the parameters of the command in

Cycles A and B.

Commands and Command Parameters

Table 18, page 31 lists the CMD bus fields that

contain the M7040N command parameters as well

as their respective cycles.

Table 17. Command Codes

CMD Code

Command

00

READ

01

WRITE

10

SEARCH

11

LEARN

Description

Reads one of the following: data array, mask array, device registers, or external

SRAM.

Writes one of the following: data array, mask array, device registers, or external

SRAM.

Searches the data array for a desired pattern using the specified register from the

global mask register array and local mask associated with each data cell.

The device has internal storage for up to 16 comparands that it can learn. The

device controller can insert these entries at the next free address (as specified by

the NFA register) using the LEARN Instruction.

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