M29W008AB データシートの表示（PDF） - STMicroelectronics
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M29W008AB Datasheet PDF : 30 Pages
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M29W008AT, M29W008AB
Table 17. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Symbol
Alt
Parameter
tAVAV
tWC Address Valid to Next Address Valid
tAVWL
tAS Address Valid to Write Enable Low
tDVWH
tDS Input Valid to Write Enable High
tELWL
tCS Chip Enable Low to Write Enable Low
tGHWL
Output Enable High to Write Enable Low
tPHPHH (1, 2) tVIDR RP Rise Time to VID
tPHWL (1)
tRSP RP High to Write Enable Low
tPLPX
tRP RP Pulse Width
tVCHEL
tVCS VCC High to Chip Enable Low
tWHDX
tDH Write Enable High to Input Transition
tWHEH
tCH Write Enable High to Chip Enable High
tWHGL
tOEH Write Enable High to Output Enable Low
tWHRL (1) tBUSY Program Erase Valid to RB Delay
tWHWL
tWPH Write Enable High to Write Enable Low
tWLAX
tAH Write Enable Low to Address Transition
tWLWH
tWP Write Enable Low to Write Enable High
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
M29W008AT / M29W008AB
80
90
VCC = 3.0V to 3.6V VCC = 3.0V to 3.6V
CL = 30pF
CL = 30pF
Min
Max
Min
Max
80
90
0
0
35
45
0
0
0
0
500
500
4
4
500
500
50
50
0
0
0
0
0
0
90
90
30
30
45
45
35
35
Unit
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles. During the input of the second command
an address within the block to be erased is given
and latched into the memory. Additional block
Erase Confirm commands and block addresses
can be written subsequently to erase other blocks
in parallel, without further Coded cycles. The
erase will start after the erase timeout period (see
Erase Timer Bit DQ3 description). Thus, additional
Erase Confirm commands for other blocks must
be given within this delay. The input of a new
Erase Confirm command will restart the timeout
period. The status of the internal timer can be
monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register status
bits.
16/30
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