M29W008AB データシートの表示（PDF） - STMicroelectronics
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M29W008AB Datasheet PDF : 30 Pages
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M29W008AT, M29W008AB
Table 18. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Symbol
Alt
Parameter
tAVAV
tWC Address Valid to Next Address Valid
tAVWL
tAS Address Valid to Write Enable Low
tDVWH
tDS Input Valid to Write Enable High
tELWL
tCS Chip Enable Low to Write Enable Low
tGHWL
Output Enable High to Write Enable Low
tPHPHH (1, 2) tVIDR RP Rise Time to VID
tPHWL (1)
tRSP RP High to Write Enable Low
tPLPX
tRP RP Pulse Width
tVCHEL
tVCS VCC High to Chip Enable Low
tWHDX
tDH Write Enable High to Input Transition
tWHEH
tCH Write Enable High to Chip Enable High
tWHGL
tOEH Write Enable High to Output Enable Low
tWHRL (1) tBUSY Program Erase Valid to RB Delay
tWHWL
tWPH Write Enable High to Write Enable Low
tWLAX
tAH Write Enable Low to Address Transition
tWLWH
tWP Write Enable Low to Write Enable High
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
M29W008AT / M29W008AB
100
120
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V
CL = 30pF
CL = 30pF
Min
Max
Min
Max
100
120
0
0
45
50
0
0
0
0
500
500
4
4
500
500
50
50
0
0
0
0
0
0
90
90
30
30
45
50
35
50
Unit
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
and Read/Reset RD instructions. Data Polling bit
DQ7 returns ’0’ while the erasure is in progress
and ’1’ when it has completed. The Toggle bit DQ2
and DQ6 toggle during the erase operation. They
stop when erase is completed. After completion
the Status Register bit DQ5 returns ’1’ if there has
been an erase failure. In such a situation, the Tog-
gle bit DQ2 can be used to determine which block
is not correctly erased. In the case of erase failure,
a Read/Reset RD instruction is necessary in order
to reset the P/E.C.
Chip Erase (CE) Instruction. This instruction
uses six write cycles. The Erase Set-up command
80h is written to address 555h on the third cycle af-
ter the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts
and the device is reset to Read Array. It is not nec-
essary to program the array with 00h first as the P/
E.C. will automatically do this before erasing it to
FFh. Read operations after the sixth rising edge of
W or E output the Status Register bits. During the
execution of the erase by the P/E.C., Data Polling
bit DQ7 returns ’0’, then ’1’ on completion. The
Toggle bits DQ2 and DQ6 toggle during erase op-
eration and stop when erase is completed. After
completion the Status Register bit DQ5 returns ’1’
if there has been an Erase Failure.
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