SAA2502 データシートの表示（PDF） - Philips Electronics

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SAA2502

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

7.2.4

LIMITED SAMPLING FREQUENCY SUPPORT FOR

INTERNAL SAMPLING CLOCKS

7.2.4.1 When sampling frequency is limited to

44.1 and/or 22.05 kHz:

In this event MCLKIN is only required to generate the

master clock frequency. Consequently the remarks on

MCLKIN frequency also apply in this special case.

7.2.4.2 When sampling frequency is limited to

48, 32, 24 and/or 16 kHz:

In this event X22IN is not required. Therefore X22IN

should be connected to VSS or VDD, but it is more efficient

to apply any available clock signal to X22IN. Because

44.1 kHz is the default initial sampling frequency it may

also be advisable to over-rule the sampling frequency after

a hard reset.

7.3 Input interface module

The input interface module handles the reception of the

coded input data stream.

The module can be configured to operate in 3 distinct

modes of operation:

• The master input mode

• The slave input mode

• The buffer controlled input mode.

Input interface mode must be stationary while the device is

in normal operation. Changing mode will result in an

(automatically generated) internal soft reset.

The inputs CD, CDVAL, CDEF and CDSY are all clocked

at the rising edge of the CDCL bit clock.

CDRQ changes at the falling edge of CDCL.

CDVAL = logic 0 indicates that CD and CDEF should be

ignored while CDVAL = logic 1 indicates that CD is a valid

coded input stream data bit (CDEF is then its error

attribute).

CDEF = logic 0 means that the value of CD may be

assumed to be reliable while CDEF = logic 1 means that

the value of CD is flagged as insecure (e.g. due to erratic

non-correctable channel behaviour). The value of CDEF

may be different for each data bit, but is combined by the

SAA2502 for every group of 8 (byte aligned) valid coded

input bits.

CDSY will only have effect when the SYMOD control flags

are set to 10 or 11. When SYMOD = 10 the valid input bit

at a rising edge of CDSY marks the start of a new byte

(when SYMOD = 11 it marks the start of a new MPEG

audio frame). Note that just the rising edge of CDSY is

important, the falling edge has no meaning.

If CDSY is used with SYMOD = 10 leading edges must be

frequent enough to assure fast byte alignment, if used with

SYMOD = 11 a leading edge must be present every frame.

Leading edges of CDSY may occur while CDVAL is

(implicitly) high. Alternatively, a situation as shown in Fig.8

is also allowed, where CDSY has a rising edge while

CDVAL is low, i.e. during invalid data. The first valid CD bit

after the rising edge of CDVAL is then interpreted as the

first byte or frame bit.

The output pin CDRQ is used to request new coded input

data.

Table 4 Signals of coded data input interface

SIGNAL

CD

CDVAL

CDEF

CDSY

CDCL

CDRQ

DIRECTION

input

input

input

input

input/output

output

FUNCTION

coded data input bit

coded data bit valid flag

coded data bit error flag

coded data sync (start of byte/frame) indication

coded data bit clock

coded data request

1997 Nov 17

11

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