87C196(1998) データシートの表示（PDF） - Intel
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87C196 Datasheet PDF : 38 Pages
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87C196CA/87C196CB - Express
Table 2. Pin Descriptions (Sheet 2 of 3)
Name
Description
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes
into a wait state mode until the next positive transition in CLKOUT occurs with READY
high. When external memory is not used, READY has no effect. The max number of wait
states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if
READY is not selected.
P5.5/BHE#/WRH#
Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects the
bank of memory that is connected to the high byte of the data bus. A0 = 0 selects the
bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide
memory can be to the low byte only (A0 = 0, BHE# = 1), to the high byte only (A0 = 1,
BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is selected, the pin
goes low if the bus cycle is writing to an odd memory location. BHE#/WRH# is only valid
during 16-bit external. Also an LSIO pin when not BHE/WRH#.
P5.4/SLPINT
Dual-function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only).
P5.3/RD#
Read signal output to external memory. RD# is active only during external memory reads
or LSIO when not used as RD#.
P5.2/WR#/WRL#
Write and Write Low output to external memory, as selected by the CCR, WR# goes low
for every external write, while WRL# goes low only for external writes where an even
byte is being written. WR#/WRL# is active during external memory writes. Also an LSIO
pin when not used as WR#/WRL#.
P5.1/INST
(CB only)
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST.
P5.0/ALE/ADV#
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV#, it goes inactive (high) at the end of the bus cycle. ADV# can be used as a chip
select for external memory. ALE/ADV# is active only during external memory accesses.
Also LSIO when not used as ALE.
PORT3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
P2.7/CLKOUT
Output of the internal clock generator. The frequency is the oscillator frequency.
CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.
P2.6/HLDA#
Bus Hold Acknowledge. Active-low output indicates that the bus controller has
relinquished control of the bus. Occurs in response to an external device asserting the
HLD# signal. Also LSIO when not used as HLDA#.
P2.5/HLDÝ
(CB only)
Bus Hold. Active-low signal indicates that an external device is requesting control of the
bus. Also LSIO when not used as HLD#.
P2.4/INTOUT#
Interrupt Output. This active-low output indicates that a pending interrupt requires use of
the external bus. Also LSIO when not used as INTOUT#.
P2.3/BREQ#
(CB only)
Bus Request. This active-low output signal is asserted during a HOLD cycle when the
bus controller has a pending external memory cycle. Also LSIO when not used as
BREQ#.
P2.2/EXTINT
A positive transition on this pin causes a maskable interrupt vector through memory
location 203CH. Also LSIO when not used as EXTINT.
P2.1/RXD
Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD.
P2.0/TXD
Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD.
PORT 1/EPA0–7
Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is
that of High Speed capture and compare. EPA0 and EPA2 have another function of
T2CLK and T2DIR of the TIMER2 timer/counter.
ADVANCE INFORMATION Datasheet
7
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