SST49LF040 データシートの表示（PDF） - Silicon Storage Technology
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SST49LF040 Datasheet PDF : 48 Pages
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4 Mbit LPC Flash
SST49LF040
Advance Information
With hardware strapping, ID bits in the address field is
included in every LPC address memory cycle. The address
bits [A22: A19] are used to select the device with proper
IDs. The ID strapping bits in the address field will be
decoded depending on where the device is mapped on the
4 GByte system memory map. See Table 2 for ID address
bits decoding. The device will compare these bits with
ID[3:0]’s strapping values. If there is a mismatch, the device
will ignore the remainder of the cycle.
TABLE 2: ID STRAPPING VALUES FOR SST49LF040
Hardware
Strapping
Address Bits [A22-A19]
Decoding1
4 GByte System Memory
Device #
ID[3:0]
Top
Bottom
0 (Boot device) 0000
1111b
0001b
1
0001
1110b
0000b
2
0010
1101b
0011b
3
0011
1100b
0010b
4
0100
1011b
0101b
5
0101
1010b
0100b
6
0110
1001b
0111b
7
0111
1000b
0110b
8
1000
0111b
1001b
9
1001
0110b
1000b
10
1010
0101b
1011b
11
1011
0100b
1010b
12
1100
0011b
1101b
13
1101
0010b
1100b
14
1110
0001b
1111b
15
1111
0000b
1110b
T2.3 562
1. Address bits A22-A19 decoding for multiple device selection
depends on whether the device is mapped from the top of the
4GB system memory map or from the bottom of the 4GB
system memory map.
(Boot Block)
Boot Device #0
(Boot Block)
Device #1
(Boot Block)
Device #2
(Boot Block)
Device #3
FFFF FFFFH
8 MByte
Memory Access
(Boot Block)
Device #14
(Boot Block)
Device #15
Device #0
FF80 0000H
FF7F FFFFH
Device #1
Device #2
Device #3
8 MByte
Register Access
Device #14
Device #15
562 ILL F01.1
FF00 0000H
FIGURE 4: BOOT CONFIGURATION FROM THE TOP
OF THE 4 GBYTE SYSTEM MEMORY MAP
©2001 Silicon Storage Technology, Inc.
11
S71213-00-000 11/01 562
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