8XL196NP データシートの表示（PDF） - Intel

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8XL196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

BHE#

BREQ#

CLKOUT

CS5#:0

Table 6. Signal Descriptions (Continued)

Type

O

Description

Byte High Enable†

During 16-bit bus cycles, this active-low output signal is asserted for word and high-

byte reads and writes to external memory. BHE# indicates that valid data is being

transferred over the upper half of the system data bus. Use BHE#, in conjunction

with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed

address/data bus), to determine which memory byte is being transferred over the

system bus:

BHE# AD0 or A0 Byte(s) Accessed

0

0

0

1

1

0

both bytes

high byte only

low byte only

BHE# shares a package pin with WRH#.

† When this pin is configured as a special-function signal (P5_MODE.5 = 1), the

chip configuration register 0 (CCR0) determines whether it functions as BHE# or

WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.

O Bus Request

This active-low output signal is asserted during a hold cycle when the bus controller

has a pending external memory cycle. When the bus-hold protocol is enabled

(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the

configuration selected through the port configuration registers (P2_MODE,

P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until

the bus-hold protocol is disabled (WSR.7 is cleared).

The microcontroller can assert BREQ# at the same time as or after it asserts

HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.

BREQ# shares a package pin with P2.4.

O Clock Output

Output of the internal clock generator. The CLKOUT frequency is ½ the internal

operating frequency (f). CLKOUT has a 50% duty cycle.

CLKOUT shares a package pin with P2.7.

O Chip-select Lines 0–5

The active-low output CSx# is asserted during an external memory cycle when the

address to be accessed is in the range programmed for chip select x. If the external

memory address is outside the range assigned to the six chip selects, no chip-

select output is asserted and the bus configuration defaults to the CS5# values.

Immediately following reset, CS0# is automatically assigned to the range FF2000–

FF20FFH (F2000–F20FFH if external).

CS5:0# share package pins with P3.5:0.

11

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