Introduction
1.3
1.4
1.5
1.6
— MPEG2 Hardware Acceleration
— ProcAmp
Clocking
• Differential Core clock of 166 MHz (BCLKP/BCLKN)
• Differential Host clock of 166 MHz (HPL_CLKINP/HPL_CLKINN)
• The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN)
• Display timings are generated from display PLLs that use a 96 MHz or 100 MHz
differential clock as reference.
• All of the above clocks are capable of tolerating Spread Spectrum clocking.
• Memory clocks generated from internal Host PLLs
• Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled
until PWROK is asserted.
Power Management Support
• Processor Core:
— Full support of ACPI C-states as implemented by the following processor C-
states: C0/C1(E)/C2(E)/C4(E)
— Enhanced Intel SpeedStep® Technology
• Thermal Management 1 (TM1) and Thermal Management 2 (TM2)
• System states: S0, S3, S4 and S5
• DMI: L0s and L1 ASPM power management capability
Package
• The processor is a Micro-FCBGA8 type of package at 22mmx22mm package size
Terminology
BGA
BLT
CRT
DDR2
DDR3
Term
(Sheet 1 of 3)
Description
Ball Grid Array
Block Level Transfer
Cathode Ray Tube
Second generation Double Data Rate SDRAM memory technology
Third generation Double Data Rate SDRAM memory technology
Datasheet
11