SST49LF008A データシートの表示（PDF） - Microchip Technology

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SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Table 4: FWH Write Cycle

Clock Field Field Contents

Cycle Name

FWH[3:0]1

FWH[3:0]

Direction

Comments

1 START

1110

IN

FWH4 must be active (low) for the part to respond. Only

the last start field (before FWH4 transitions high) should

be recognized. The START field contents indicate a FWH

memory Read cycle.

2 IDSEL 0000 to 1111

IN

Indicates which SST49LF008A device should respond.

If the IDSEL (ID select) field matches the value

ID[3:0], then that particular device will respond to the

whole bus cycle.

3-9 IMADDR

YYYY

IN

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

10 IMSIZE 0000 (1 byte)

IN

This size field indicates how many bytes will be trans-

ferred during multi-byte operations. The FWH only

supports single-byte writes. IMSIZE=0000b

11 DATA

YYYY

IN

This field is the least-significant nibble of the data byte.

This data is either the data to be programmed into the

flash memory or any valid flash command.

12 DATA

YYYY

IN

This field is the most-significant nibble of the data byte.

13 TAR0

1111

IN then Float

In this clock cycle, the master (Intel ICH) has driven the

then float bus to all ‘1’s and then floats the bus prior to

the next clock cycle. This is the first part of the bus “turn-

around cycle.”

14

TAR1

1111 (float) Float then OUT The SST49LF008A takes control of the bus during this

cycle. During the next clock cycle it will be driving the

“sync” data.

15 RSYNC

0000

OUT

The SST49LF008A outputs the values 0000, indicating

that it has received data or a flash command.

16 TAR0

1111

OUT then Float

In this clock cycle, the SST49LF008A has driven the bus

to all then float ‘1’s and then floats the bus prior to the

next clock cycle. This is the first part of the bus “turn-

around cycle.”

17 TAR1

1111 (float)

Float then IN The master (Intel ICH) resumes control of the bus during this

cycle.

1. Field contents are valid on the rising edge of the present clock cycle.

T4.4 25085

CLK

FWH4

FWH[3:0]

STR IDS

Figure 7: Write Waveforms

IMADDR

IMS

DATA

TAR RSYNC

TAR

1161 F10.0

©2011 Silicon Storage Technology, Inc.

11

DS25085A

10/11

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