BCM2835 データシートの表示（PDF） - Broadcom Corporation

部品番号

コンポーネント説明

メーカー

BCM2835

BCM2835 ARM Peripherals

Broadcom Corporation 

2.2.1 Mini UART implementation details.

The UART1_CTS and UART1_RX inputs are synchronised and will take 2 system clock

cycles before they are processed.

The module does not check for any framing errors. After receiving a start bit and 8 (or 7)

data bits the receiver waits for one half bit time and then starts scanning for the next start bit.

The mini UART does not check if the stop bit is high or wait for the stop bit to appear. As a

result of this a UART1_RX input line which is continuously low (a break condition or an

error in connection or GPIO setup) causes the receiver to continuously receive 0x00

symbols.

The mini UART uses 8-times oversampling. The Baudrate can be calculated from:

baudrate

=

system _ clock

8 * (baudrate _

_ freq

reg + 1)

If the system clock is 250 MHz and the baud register is zero the baudrate is 31.25 Mega

baud. (25 Mbits/sec or 3.125 Mbytes/sec). The lowest baudrate with a 250 MHz system

clock is 476 Baud.

When writing to the data register only the LS 8 bits are taken. All other bits are ignored.

When reading from the data register only the LS 8 bits are valid. All other bits are zero.

2.2.2 Mini UART register details.

AUX_MU_IO_REG Register (0x7E21 5040)

SYNOPSIS

The AUX_MU_IO_REG register is primary used to write data to and read data from the

UART FIFOs.

If the DLAB bit in the line control register is set this register gives access to the LS 8 bits

of the baud rate. (Note: there is easier access to the baud rate register)

Bit(s) Field Name

31:8

7:0 LS 8 bits

Baudrate

read/write,

DLAB=1

7:0 Transmit data

write,

DLAB=0

7:0 Receive data

read,

DLAB=0

Description

Reserved, write zero, read as don’t care

Access to the LS 8 bits of the 16-bit baudrate

register.

(Only If bit 7 of the line control register (DLAB bit)

is set)

Data written is put in the transmit FIFO (Provided it

is not full)

(Only If bit 7 of the line control register (DLAB bit)

is clear)

Data read is taken from the receive FIFO (Provided

it is not empty)

(Only If bit 7 of the line control register (DLAB bit)

is clear)

Type Reset

R/W 0

W0

R0

06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW

© 2012 Broadcom Corporation. All rights reserved

Page 11

Share Link: