FS6377 データシートの表示（PDF） - ON Semiconductor

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FS6377

Programmable 3-PLL Clock Generator IC

ON Semiconductor 

FS6377

6.2 Power-Down

All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is

asserted.

Table 4: Power-Down Bits

Name

Description

PDPLL_A

(Bit 21)

Power-Down PLL A

Bit = 0

Bit = 1

Power on

Power off

Power-Down PLL B

PDLL_B

(Bit 45)

Bit = 0

Bit = 1

Power on

Power off

Power-Down PLL C

PDLL_C

(Bit 69)

Bit = 0

Bit = 1

Power on

Power off

Reserved

(Bit 69)

(0)

Set these reserved bits to zero (0)

Power-Down POST Divider A

PDPOSTA Bit = 0

(Bit 120)

Bit = 1

Power on

Power off

Power-Down POST Divider B

PDPOSTB Bit = 0

(Bit 121)

Bit = 1

Power on

Power off

PDPOSTC

(Bit 122)

Power-Down POST Divider C

Bit = 0

Bit = 1

Power on

Power off

Power-Down POST Divider D

PDPOSTD Bit = 0

(Bit 123)

Bit = 1

Power on

Power off

Table 5: Divider Control Bits

Name

Description

REFDIV_A[7:0]

(Bits 7-0)

Reference Divider A (NR)

REFDIV_B[7:0]

(Bits 31-24)

Reference Divider B (NR)

REFDIV_C1[7:0] Reference Divider C1 (NR)

(Bits 55-48)

selected when the SEL_CD pin = 0

REFDIV_C2[7:0] Reference Divider C2 (NR)

(Bits 79-72)

selected when the SEL_CD pin = 1

Feedback Divider A (NF)

FBKDIV_A[10:0] FBKDIV_A[2:0]

(Bits 18-8)

FBKDIV_A[10:3]

A-Counter value

M-Counter value

Feedback Divider B (NF)

FBKDIV_B[10:0] FBKDIV_B[2:0]

(Bits 42-32)

FBKDIV_B[10:3]

A-Counter value

M-Counter value

Feedback Divider C1 (NF)

selected when the SEL_CD pin = 0

FBKDIV_C1[10:0] FBKDIV_C1[2:0]

(Bits 66-56)

FBKDIV_C1[10:3]

A-Counter value

M-Counter value

Feedback Divider C2 (NF)

selected when the SEL_CD pin = 1

FBKDIV_C2[10:0] FBKDIV_C2[2:0] A-Counter value

(Bits 90-80)

FBKDIV_C2[10:3] M-Counter value

Rev. 4 | Page 11 of 24 | www.onsemi.com

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