INTEL386 データシートの表示（PDF） - Intel

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INTEL386

Intel386 SX MICROPROCESSOR

Intel 

Intel386TM SX MICROPROCESSOR

2 3 Memory Organization

Memory on the Intel386 SX Microprocessor is divid-

ed into 8-bit quantities (bytes) 16-bit quantities

(words) and 32-bit quantities (dwords) Words are

stored in two consecutive bytes in memory with the

low-order byte at the lowest address Dwords are

stored in four consecutive bytes in memory with the

low-order byte at the lowest address The address of

a word or dword is the byte address of the low-order

byte

In addition to these basic data types the Intel386 SX

Microprocessor supports two larger units of memory

pages and segments Memory can be divided up

into one or more variable length segments which

can be swapped to disk or shared between pro-

grams Memory can also be organized into one or

more 4K byte pages Finally both segmentation and

paging can be combined gaining the advantages of

both systems The Intel386 SX Microprocessor sup-

ports both pages and segmentation in order to pro-

vide maximum flexibility to the system designer

Segmentation and paging are complementary Seg-

mentation is useful for organizing memory in logical

modules and as such is a tool for the application

programmer while pages are useful to the system

programmer for managing the physical memory of a

system

ADDRESS SPACES

The Intel386 SX Microprocessor has three types of

address spaces logical linear and physical A

logical address (also known as a virtual address)

consists of a selector and an offset A selector is the

contents of a segment register An offset is formed

by summing all of the addressing components

(BASE INDEX DISPLACEMENT) discussed in sec-

tion 2 4 Addressing Modes into an effective ad-

dress This effective address along with the selector

is known as the logical address Since each task on

the Intel386 SX Microprocessor has a maximum of

16K (214 b1) selectors and offsets can be 4 giga-

bytes (with paging enabled) this gives a total of 246

bits or 64 terabytes of logical address space per

task The programmer sees the logical address

space

The segmentation unit translates the logical ad-

dress space into a 32-bit linear address space If the

paging unit is not enabled then the 32-bit linear ad-

dress is truncated into a 24-bit physical address

The physical address is what appears on the ad-

dress pins

The primary differences between Real Mode and

Protected Mode are how the segmentation unit per-

forms the translation of the logical address into the

linear address size of the address space and pag-

ing capability In Real Mode the segmentation unit

shifts the selector left four bits and adds the result to

the effective address to form the linear address

This linear address is limited to 1 megabyte In addi-

tion real mode has no paging capability

Protected Mode will see one of two different ad-

dress spaces depending on whether or not paging

is enabled Every selector has a logical base ad-

dress associated with it that can be up to 32 bits in

length This 32-bit logical base address is added to

the effective address to form a final 32-bit linear

address If paging is disabled this final linear ad-

dress reflects physical memory and is truncated so

that only the lower 24 bits of this address are used

to address the 16 megabyte memory address space

If paging is enabled this final linear address reflects

a 32-bit address that is translated through the pag-

ing unit to form a 16-megabyte physical address

The logical base address is stored in one of two

operating system tables (i e the Local Descriptor

Table or Global Descriptor Table)

Figure 2 3 shows the relationship between the vari-

ous address spaces

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