MCF51JF128(2011) データシートの表示（PDF） - Freescale Semiconductor

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MCF51JF128
(Rev.:2011)

Embedded - Microcontrollers

Freescale Semiconductor 

Clock modules

Table 13. MCG specifications (continued)

Symbol Description

Min.

fdco

DCO output

Low range (DRS=00)

20

frequency range

640 × ffll_ref

Mid range (DRS=01)

40

1280 × ffll_ref

Mid-high range (DRS=10)

60

1920 × ffll_ref

High range (DRS=11)

80

2560 × ffll_ref

fdco_t_DMX3 DCO output

2

frequency

Low range (DRS=00)

—

732 × ffll_ref

Mid range (DRS=01)

—

1464 × ffll_ref

Mid-high range (DRS=10)

—

2197 × ffll_ref

High range (DRS=11)

—

2929 × ffll_ref

Jcyc_fll FLL period jitter

—

Jacc_fll FLL accumulated jitter of DCO output over a 1µs

—

time window

tfll_acquire FLL target frequency acquisition time

—

PLL

fvco

VCO operating frequency

48.0

Ipll

PLL operating current

• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

—

2 MHz, VDIV multiplier = 48)

Ipll

PLL operating current

• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

—

2 MHz, VDIV multiplier = 24)

fpll_ref PLL reference frequency range

2.0

Jcyc_pll PLL period jitter

• fvco = 48 MHz

—

• fvco = 100 MHz

—

Typ.

20.97

41.94

62.91

83.89

23.99

47.97

71.99

95.98

TBD

TBD

—

—

1060

600

—

120

50

Max.

25

50

75

100

—

—

—

—

TBD

TBD

1

100

—

—

4.0

—

—

Jacc_pll

PLL accumulated jitter over 1µs window

• fvco = 48 MHz

• fvco = 100 MHz

—

1350

—

—

600

—

Table continues on the next page...

Unit

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

ps

ps

ms

MHz

µA

µA

MHz

ps

ps

ps

ps

Notes

2, 3

4, 5

6

6

7

8

8

9, 10

9, 10

MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.

22

Preliminary

Freescale Semiconductor, Inc.

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