MCF51JF128(2011) データシートの表示（PDF） - Freescale Semiconductor

部品番号

コンポーネント説明

メーカー

MCF51JF128
(Rev.:2011)

Embedded - Microcontrollers

Freescale Semiconductor 

Clock modules

Table 14. Oscillator DC electrical specifications (continued)

Symbol

Vpp5

Description

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

Min.

—

—

—

—

Typ.

0.6

VDD

0.6

VDD

Max.

—

—

—

—

Unit

Notes

V

V

V

V

1. VDD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.

4. When low power mode is selected, RF is integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other devices.

6.3.2.2 Oscillator frequency specifications

Table 15. Oscillator frequency specifications

Symbol

fosc_lo

fosc_hi_1

fosc_hi_2

fec_extal

tdc_extal

tcst

Description

Oscillator crystal or resonator frequency — low

frequency mode (MCG_C2[RANGE]=00)

Oscillator crystal or resonator frequency — high

frequency mode (low range)

(MCG_C2[RANGE]=01)

Oscillator crystal or resonator frequency — high

frequency mode (high range)

(MCG_C2[RANGE]=1x)

Input clock frequency (external clock mode)

Input clock duty cycle (external clock mode)

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

Min.

32

1

8

—

40

—

—

—

—

Typ.

—

—

—

—

50

750

250

0.6

1

Max.

40

8

Unit

kHz

MHz

32

MHz

50

MHz

60

%

—

ms

—

ms

—

ms

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL

2. Proper PC board layout procedures must be followed to achieve specifications.

Notes

1

2, 3

MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.

Freescale Semiconductor, Inc.

Preliminary

25

Share Link: