NAND04GW3C2N1E データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
NAND04GW3C2N1E Datasheet PDF : 51 Pages
| |||
NAND04GA3C2A, NAND04GW3C2A
3
Signal Descriptions
3 Signal Descriptions
See Figure 1: Logic Block Diagram, and Table 3: Signal Names, for a brief overview of the
signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
3.3
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.4
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes
high, vIH, while the device is busy, the device remains selected and does not go into standby
mode.
3.5
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during Read operations. Data
is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.6
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
13/51
Share Link: 