CXD3500R データシートの表示（PDF） - Sony Semiconductor
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CXD3500R Datasheet PDF : 73 Pages
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CXD3500R
Each control data is described in detail below.
The following descriptions define the width of one dot clock as "clk".
PLLP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The
data is 12 bits and the frequency division ratio can be set up to 4096. However, the internal logic circuits of this
TG operate at 1/2 clock, so the PLLP0 setting is invalid. When N is an odd number, use an external frequency
divider.
The actual frequency division ratio should be set as follows.
Number of clk for the horizontal period – 2 = Actual number of dots set
Examples of settings for major modes are shown below.
Note) When using an external frequency divider (serial data HR is L), these settings are not necessary. (They
can also be set to all L.)
1) Macintosh16 (832 × 624)
PLLP setting value = 1152 (horizontal period) – 2 → 1150 (LHLLLHHHHHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L H L L L H H H H H H L
2) SVGA (800 × 600)
PLLP setting value = 1056 (horizontal period) – 2 → 1054 (LHLLLLLHHHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L H L L L L L L H H H L ∗ VESA SVGA60
3) VGA (640 × 480)
PLLP setting value = 800 (horizontal period) – 2 → 798 (LLHHLLLHHHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L L H H L L L H H H H L ∗ VGA60
4) PC98 (640 × 400)
PLLP setting value = 848 (horizontal period) – 2 → 846 (LLHHLHLLHHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L L H H L H L L H H H L
5) NTSC double speed (640 × 480)
PLLP setting value = 1560 (horizontal period) – 2 → 1558 (LHHLLLLHLHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L H H L L L L H L H H L
6) PAL double speed (762 × 572)
PLLP setting value = 1880 (horizontal period) – 2 → 1878 (LHHHLHLHLHHL: LSB)
PLLP 11 10 9 8 7 6 5 4 3 2 1 0
Setting data L H H H L H L H L H H L
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