CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

HP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of with

12 bits is possible using the front edge of HSYNC as the reference. The HP setting range is from 0 to (N – 1).

However, do not set HP to the number of frequency divisions N or higher, as the various pulses will not be

output.

The horizontal direction timing is interlinked using the falling edges of ENB1 and 2 as the reference. The

following pulses are interlinked according to the HP11 to 0 setting.

HST, HCK1, HCK2, ENB1, ENB2, PCG, PRG, CLP, BLK, VD, VCK transition point, FRP transition point,

XFRP transition point, BLK transition point and VD transition point

Thp

Image display period

HSYNC

HST

HDN

Thp: Timing from the front edge of HSYNC to the HST pulse

HSTP5 to 0: LLLLL, HDNPOL: H

Minimum Thp setting values for each mode

PLSSL2, 1, 0

LLL

LLH

LHL

LHH

HLL

HLH

HHL

HHH

Thp

72 clk

92 clk

118 clk

146 clk

178 clk

188 clk

204 clk

232 clk

∗ HSTP5, 4, 3, 2, 1, 0: All L

Note) The time from HST until image display starts differs for each panel and its display area switching mode.

In modes which apply a reset at the front edge of HSYNC (HR: L), the HDN pulse transition point is

delayed by several dots relative to HSYNC. In these modes, Thp in the table above indicates the value

using the HDN pulse transition point as the reference.

6 to 10 clk

HSYNC

HDN

Reference: HDN transition point

– 14 –

HDNPOL: H

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