CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

PRGD4, 3, 2, 1, 0

These bits adjust the PRG pulse fall position in 2-dot units.

However, the PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL.

The PRG pulse rise position is the same as the FRP pulse transition point. (interlinked with FRPP3, 2, 1, 0)

The PRGD4, 3, 2, 1, 0 setting range is shown in the table below.

ENB1, 2

Tprd

PRG

FRP

Tpru setting range

PLSSL2, 1, 0

PCGD4∗, 3, 2, 1, 0

LLLLL LHHHH

PCGD4∗, 3, 2, 1, 0

HLLLL HHHHH

LLL

62 clk

92 clk

62 clk

92 clk

LLH

82 clk

112 clk

82 clk

112 clk

LHL

108 clk

138 clk

108 clk

138 clk

LHH

136 clk

166 clk

136 clk

166 clk

HLL

168 clk

198 clk

168 clk

198 clk

HLH

136 clk

166 clk

182 clk

212 clk

HHL

142 clk

172 clk

196 clk

226 clk

HHH

162 clk

192 clk

222 clk

252 clk

∗: The PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL.

PCG

This bit selects the new and old PCG pulse timing.

When PCG is H, the PCGU2 to 0 setting shown on the previous page is selected. (new timing)

When PCG is L, the PCG pulse rise position is interlinked with the FRP pulse transition point. (old timing)

Set to match the timing specifications of the LCD panel.

Set PCG to H for SVGA panels that support two-step precharge, and to L for other panels.

FRP

PCG: H

PCG: L

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