CXD3500R データシートの表示（PDF） - Sony Semiconductor

部品番号

コンポーネント説明

メーカー

CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

VP7, 6, 5, 4, 3, 2, 1, 0

These bits set the vertical display start position. The minimum adjustment width is 1H of the output signal, and

adjustment of up to 256H with 8 bits is possible using the front edge of VSYNC as the reference.

In interlace signal double-speed mode, the vertical display start position can be set within a width of 1H relative

to the double-speed converted signal.

a) Non-interlace

VSYNC

Minimum adjustment width

Tvp

HSYNC

VST

VCK

b) When using an interlace double-speed controller

ODD field

Tvp

VSYNC

HSYNC

VST

Minimum adjustment width

VCK

EVEN field

Tvp

VSYNC

HSYNC

VST

VCK

Minimum and maximum Tvp setting values

VP

Min.

Max.

76543210

LLLLLLLL

HHHHHHHH

4H

259H

Note) The time from VST until image display starts differs for each panel.

Also see the data sheets of the used panels.

– 15 –

Share Link: