M36W0R5020B0 データシートの表示（PDF） - STMicroelectronics

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M36W0R5020B0

32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package

STMicroelectronics 

M36W0R5020T0, M36W0R5020B0

Figure 11. SRAM Write AC Waveforms, E1S or E2S Controlled

tAVAV

A0-A17

VALID

tAVE1H

tAVE2L

tAVE1L

tE1LE1H

E1S

tE1HAX

E2S

WS

UBS, LBS

tAVE2H

tE2HE2L

tWLE1H

tWLE2L

tBLE1H

tBLE2L

tE2LAX

GS

DQ0-DQ15

tGHDZ

Note 2

tDVE1H

tDVE2L

tE1HDX

tE2LDX

INPUT VALID

Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.

2. The I/O pins are in output mode and input signals should not be applied.

3. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

4. UBS, LBS means both UBS and LBS.

AI09883

18/26

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