M36W0R5020B0 データシートの表示（PDF） - STMicroelectronics

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M36W0R5020B0

32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package

STMicroelectronics 

M36W0R5020T0, M36W0R5020B0

Figure 13. SRAM Write AC Waveforms, WS Controlled with GS Low

A0-A17

E1S

tAVAV

VALID

tAVWH

tE1LWH

tE2HWH

tWHAX

E2S

UBS, LBS

WS

DQ0-DQ15

tAVWL

tWLDZ

Note 1

tBLWH

tWLWH

tDVWH

tWHDX

tWHDZ

INPUT VALID

Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.

2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

3. UBS, LBS means both UBS and LBS.

Figure 14. SRAM Write AC Waveform, UBS and LBS Controlled GS Low

tAVAV

A0-A17

VALID

tAVBH

tE1LBH

tE2HBH

E1S

AI09885

E2S

UBS, LBS

WS

DQ0-DQ15

tAVBL

Note 2

tBLBH

tBHAX

tWLBH

tDVBH

tBHDX

INPUT VALID

Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

2. The I/O pins are in output mode and input signals should not be applied.

3. UBS, LBS means both UBS and LBS.

AI09886

20/26

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