M29W008AB データシートの表示（PDF） - STMicroelectronics

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M29W008AB

8 Mbit (1Mb x8, Boot Block) Low Voltage Single Supply Flash Memory

STMicroelectronics 

M29W008AT, M29W008AB

Table 11. Polling and Toggle Bits

Mode

DQ7 DQ6 DQ2

Program

DQ7 Toggle 1

Erase

0 Toggle Note 1

Erase Suspend Read

(in Erase Suspend

1

1 Toggle

block)

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

Erase Suspend Program DQ7 Toggle N/A

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to '1' during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to '1' dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to '1', DQ2 will toggle if the faulty block

is addressed.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a '1' to a lo-

cation that is previously programmed to '0'. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to '0'.

Erase Timer Bit (DQ3). This bit is set to '0' by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µs to 90µs, DQ3 returns

to '1'.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address 555h during the

first cycle. During the second cycle the Coded cy-

cles consist of writing the data 55h at address

2AAh. A0 to A11 are valid, other address lines are

’don’t care’. The Coded cycles happen on first and

second cycles of the command write or on the

fourth and fifth cycles.

Instructions

See Table 9.

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read. A wait state of 10µs is nec-

essary after Read/Reset prior to any valid read if

the memory was in an Erase mode when the RD

instruction is given. The Read/Reset command is

not accepted during Erase and Erase Suspend.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address 555h for

command set-up. A subsequent read will output

the manufacturer code and the device code or the

block protection status depending on the levels of

A0 and A1. The manufacturer code, 20h, is output

when the addresses lines A0 and A1 are Low, the

device code, EAh for Top Boot, EBh for Bottom

Boot is output when A0 is High with A1 Low.

The AS instruction also allows access to the block

protection status. After giving the AS instruction,

A0 and A6 are set to VIL with A1 at VIH, while A13-

A19 define the address of the block to be verified.

A read in these conditions will output a 01h if the

block is protected and a 00h if the block is not pro-

tected.

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 555h on the third cycle after two

Coded cycles. A fourth write operation latches the

Address on the falling edge of W or E and the Data

to be written on the rising edge and starts the P/

E.C. Read operations output the Status Register

bits after the programming has started. Memory

programming is made only by writing '0' in place of

'1'. Status bits DQ6 and DQ7 determine if pro-

gramming is on-going and DQ5 allows verification

of any possible error. Programming at an address

not in blocks being erased is also possible during

erase suspend. In this case, DQ2 will toggle at the

address being programmed.

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