CS61304A データシートの表示（PDF） - Cirrus Logic

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CS61304A

T1/E1 Line Interface

Cirrus Logic 

CS61304A

CS61304A

Percent of

nominal

peak

voltage

120

110

100

90

80

269 ns

244 ns

194 ns

50

10

Nominal Pulse

0

-10

-20

219 ns

488 ns

Figure 9. Mask of the Pulse at the 2048 kbps Interface

Transmit All Ones Select

The transmitter provides for all ones insertion at

the frequency of TCLK. Transmit all ones is se-

lected when TAOS goes high, and causes

continuous ones to be transmitted on the line

(TTIP and TRING). In this mode, the TPOS and

TNEG (or TDATA) inputs are ignored. If Remote

Loopback is in effect, any TAOS request will be

ignored.

Receiver

The receiver extracts data and clock from an AMI

(Alternate Mark Inversion) coded signal and out-

puts clock and synchronized data. The receiver is

sensitive to signals over the entire range of

ABAM cable lengths and requires no equalization

or ALBO (Automatic Line Build Out) circuits.

The signal is received on both ends of a center-

tapped, center-grounded transformer. The

transformer is center tapped on the IC side. The

clock and data recovery circuit exceeds the jitter

tolerance specifications of Publications 43802,

43801, AT&T 62411, TR-TSY-000170, and

CCITT REC. G.823.

A block diagram of the receiver is shown in Fig-

ure 10. The two leads of the transformer (RTIP

and RRING) have opposite polarity allowing the

receiver to treat RTIP and RRING as unipolar sig-

nals. Comparators are used to detect pulses on

RTIP and RRING. The comparator thresholds are

dynamically established at a percent of the peak

level (50% of peak for E1, 65% of peak for T1;

with the slicing level selected by LEN2/1/0 in-

puts).

The leading edge of an incoming data pulse trig-

gers the clock phase selector. The phase selector

chooses one of the 13 available phases which the

delay line produces for each bit period. The out-

For coaxial cable,

75Ω l o a d a nd

transformer specified

in Application Section.

For shielded twisted

pair, 120Ω load and

transformer specified

in Application Section.

Nominal peak voltage of a mark (pulse)

2.37 V

3V

Peak voltage of a space (no pulse)

0 ±0.237 V

0 ±0.30 V

Nominal pulse width

244 ns

Ratio of the amplitudes of positive and negative

pulses at the center of the pulse interval

0.95 to 1.05*

Ratio of the widths of positive and negative

pulses at the nominal half amplitude

0.95 to 1.05*

* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer

primary as shown in Figures A1, A2 and A3.

Table 4. CCITT G.703 Specifications

DS156PFP1 2

1111

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