CXD3500R データシートの表示（PDF） - Sony Semiconductor

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コンポーネント説明

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

XCLR pin

The CXD3500R should be forcibly reset during power on in order to initialize the serial transfer block and other

internal circuits. At this time, the serial interface circuit is reset to the initial status (preset status). See page 38

for the preset settings.

Serial transfer operation

1. Control method

The CXD3500R operation timing is controlled by serial data.

The control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of

SCLK. This loading operation starts from the fall of SCTR and is completed at the next rise of SCTR.

Serial transfer timing

SCTR

SCLK

SDAT

D15 D14 D13 D12 D11 D10 D9 D8

Address

D7 D6 D5 D4 D3 D2 D1 D0

Data

– 11 –

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